// **************************************************************
// COPYRIGHT(c)2020, Xidian University
// All rights reserved.
//
// IP LIB INDEX : 
// IP Name      : 
//                
// File name    :
// Module name  : 
// Full name    :
//
// Author       :  Hbing 
// Email        :  2629029232@qq.com
// Data         :  2020/8/24
// Version      :  V 1.0 
// 
//Abstract      :
// Called by    :  Father Module
// 
// Modification history
// ------------------------------------------------------------------------------------------------------
// 
//  
// *********************************************************************
`include "top_define.v"
// *******************
// TIMESCALE
// ******************* 
`timescale 1ns/1ps 

// *******************
// DESCRIPTION
// *******************
// 暂定总BD数量为4096个--12bit位宽--2Mbit
// 
//*******************
//DEFINE(s)
//*******************
//`define UDLY 1    //Unit delay, for non-blocking assignments in sequential logic

//*******************
//DEFINE MODULE PORT
module queue_infor_management(
	//sysrem input/output
	input  wire 		clk  ,
	input  wire 		rst_n,
	//with schedule_enqueue
	(*mark_debug = "true"*) input  wire 		enqueue_head_infor_wr_en  ,
	(*mark_debug = "true"*) input  wire [ 5:0]  enqueue_head_infor_wr_addr,
	(*mark_debug = "true"*) input  wire [31:0]  enqueue_head_infor_wr_data,
	(*mark_debug = "true"*) output wire [31:0]  enqueue_head_infor_rd_data,

	(*mark_debug = "true"*) input  wire 		enqueue_tail_infor_wr_en  ,
	(*mark_debug = "true"*) input  wire [ 5:0]  enqueue_tail_infor_wr_addr,
	(*mark_debug = "true"*) input  wire [15:0]  enqueue_tail_infor_wr_data,
	(*mark_debug = "true"*) output wire [15:0]  enqueue_tail_infor_rd_data,

	(*mark_debug = "true"*) input  wire 		enqueue_length_infor_wr_en  ,
	(*mark_debug = "true"*) input  wire [ 5:0]  enqueue_length_infor_wr_addr,
	(*mark_debug = "true"*) input  wire [15:0]  enqueue_length_infor_wr_data,
	(*mark_debug = "true"*) output wire [15:0]  enqueue_length_infor_rd_data,
	// output reg  		queue_length_wren_b,
	// output wire [ 5:0]  queue_length_addr_b,
	// output reg  [15:0]  queue_length_din_b ,

	(*mark_debug = "true"*) input  wire 		enqueue_node_length_wr_en  ,
	(*mark_debug = "true"*) input  wire [ 2:0]  enqueue_node_length_wr_addr,
	(*mark_debug = "true"*) input  wire [15:0]  enqueue_node_length_wr_data,
	(*mark_debug = "true"*) output wire [15:0]  enqueue_node_length_rd_data,
	// output reg  		node_length_wren_b,
	// output wire [ 2:0]  node_length_addr_b,
	// output reg  [15:0]  node_length_din_b ,
	//with schedule_dequeue
	(*mark_debug = "true"*) input  wire 		dequeue_head_infor_wr_en  ,
	(*mark_debug = "true"*) input  wire [ 5:0]  dequeue_head_infor_wr_addr,
	(*mark_debug = "true"*) input  wire [31:0]  dequeue_head_infor_wr_data,
	(*mark_debug = "true"*) output wire [31:0]  dequeue_head_infor_rd_data,

	(*mark_debug = "true"*) input  wire 		dequeue_tail_infor_wr_en  ,
	(*mark_debug = "true"*) input  wire [ 5:0]  dequeue_tail_infor_wr_addr,
	(*mark_debug = "true"*) input  wire [15:0]  dequeue_tail_infor_wr_data,
	// output wire [15:0]  dequeue_tail_infor_rd_data,

	(*mark_debug = "true"*) input  wire 		dequeue_length_infor_wr_en  ,
	(*mark_debug = "true"*) input  wire [ 5:0]  dequeue_length_infor_wr_addr,
	(*mark_debug = "true"*) input  wire [15:0]  dequeue_length_infor_wr_data,
	(*mark_debug = "true"*) output wire [15:0]  dequeue_length_infor_rd_data,
	// output reg  		queue_length_wren_a,
	// output wire [ 5:0]  queue_length_addr_a,
	// output reg  [15:0]  queue_length_din_a ,

	(*mark_debug = "true"*) input  wire 		dequeue_node_length_wr_en  ,
	(*mark_debug = "true"*) input  wire [ 2:0]  dequeue_node_length_wr_addr,
	(*mark_debug = "true"*) input  wire [15:0]  dequeue_node_length_wr_data,
	(*mark_debug = "true"*) output wire [15:0]  dequeue_node_length_rd_data
	// output reg  		node_length_wren_a,
	// output wire [ 2:0]  node_length_addr_a,
	// output reg  [15:0]  node_length_din_a 

    //with bus_master_rx
    // input  wire         enqueue_indicate_length_wr_en  ,
    // input  wire [ 2:0]  enqueue_indicate_length_wr_addr,
    // input  wire [47:0]  enqueue_indicate_length_wr_data,
    // output reg  [47:0]  enqueue_indicate_length_rd_data,
    // output reg          indicate_length_wren_b,
    // output wire [ 2:0]  indicate_length_addr_b,
    // output reg  [47:0]  indicate_length_din_b ,
    // //with tx_request_gen
    // input  wire         dequeue_indicate_length_wr_en  ,
    // input  wire [ 2:0]  dequeue_indicate_length_wr_addr,
    // input  wire [47:0]  dequeue_indicate_length_wr_data,
    // output reg  [47:0]  dequeue_indicate_length_rd_data,
    // output reg          indicate_length_wren_a,
    // output wire [ 2:0]  indicate_length_addr_a,
    // output reg  [47:0]  indicate_length_din_a 
	);

//*******************
//DEFINE PARAMETER
//*******************
//Parameter(s) 
//
//queue_head_infor_ram--32*33
// _ _ _ _ 16 _ _ _ _ _ _ _ _ _16_ _ _ _ _
//|       31~15    |          15~0        |
//|__head_BD_addr__|___head_frame_length__|
//
//queue_tail_infor_ram--16*33
// _ _ _ _ 16 _ _ _ 
//|       15~0     |
//|__head_BD_addr__|
//
//queue_length_infor_ram--16*33
// _ _ _ _ 16 _ _ _ 
//|       15~0     |
//|_enqueue_BD_num_|
//
//node_length_ram--16*33
// _ _ _ _ 16 _ _ _ 
//|       15~0     |
//|_enqueue_BD_num_|
//
//*********************
//INNER SIGNAL DECLARATION
//*********************
//REGS
//处理队尾更新冲突
// reg        queue_tail_wren_a;
// reg [ 6:0] queue_tail_waddr_a;
// reg [15:0] queue_tail_din_a ;
// reg        queue_tail_wren_b;
// reg [ 6:0] queue_tail_waddr_b;
// reg [15:0] queue_tail_din_b ;
//处理队长更新冲突
// reg        queue_length_wren_a_r;
// reg        queue_length_wren_b_r;
// reg [ 5:0] queue_length_addr_a_r;
// reg [ 5:0] queue_length_addr_b_r;
// reg [15:0] queue_length_din_a_r ;
// reg [15:0] queue_length_din_b_r ;
// //处理节点长度更新冲突
// reg        node_length_wren_a_r;
// reg        node_length_wren_b_r;
// reg [ 2:0] node_length_addr_a_r;
// reg [ 2:0] node_length_addr_b_r;
// reg [15:0] node_length_din_a_r ;
// reg [15:0] node_length_din_b_r ;
// //处理物理队长更新冲突
// reg        indicate_length_wren_a_r;
// reg        indicate_length_wren_b_r;
// reg [ 2:0] indicate_length_addr_a_r;
// reg [ 2:0] indicate_length_addr_b_r;
// reg [47:0] indicate_length_din_a_r ;
// reg [47:0] indicate_length_din_b_r ;

//WIRES
//队长读数据
// wire [15:0] queue_length_dout_a;
// wire [15:0] queue_length_dout_b;
// //节点长度读数据
// wire [15:0] node_length_dout_a;
// wire [15:0] node_length_dout_b;
//物理队长读数据
// wire [47:0] indicate_length_dout_a;
// wire [47:0] indicate_length_dout_b;

//队首更新使能冲突处理
wire enqueue_head_infor_wr_en_a;
wire dequeue_head_infor_wr_en_b;
assign enqueue_head_infor_wr_en_a = enqueue_head_infor_wr_en;
assign dequeue_head_infor_wr_en_b = ((enqueue_head_infor_wr_en && dequeue_head_infor_wr_en) && (enqueue_head_infor_wr_addr == dequeue_head_infor_wr_addr)) ? 1'b0:dequeue_head_infor_wr_en ;
//队尾使能冲突处理
wire dequeue_tail_wr_en_b;
assign dequeue_tail_wr_en_b = ((~enqueue_tail_infor_wr_en) & dequeue_tail_infor_wr_en);
//*********************
//INSTANTCE MODULE
//*********************
//队首信息RAM
// queue_infor_ram_w32_d33 U_queue_head_infor(
//     .clka                 (clk                            ), // input clka
//     .wea                  (enqueue_head_infor_wr_en_a     ), // input [0 : 0] wea
//     .addra                (enqueue_head_infor_wr_addr     ), // input [5 : 0] addra
//     .dina                 (enqueue_head_infor_wr_data     ), // input [31 : 0] dina
//     .douta                (enqueue_head_infor_rd_data     ), // output [31 : 0] douta
//     .clkb                 (clk                            ), // input clkb
//     .web                  (dequeue_head_infor_wr_en_b     ), // input [0 : 0] web
//     .addrb                (dequeue_head_infor_wr_addr     ), // input [5 : 0] addrb
//     .dinb                 (dequeue_head_infor_wr_data     ), // input [31 : 0] dinb
//     .doutb                (dequeue_head_infor_rd_data     )
//     // output [31 : 0] doutb
// 	);
queue_infor_ram_w32_d33_reg U_queue_head_infor(
    .clk                  (clk                            ), // input clka
    .rst_n                (rst_n                          ), // input rst_n    
    .wea                  (enqueue_head_infor_wr_en_a     ), // input [0 : 0] wea
    .addra                (enqueue_head_infor_wr_addr     ), // input [5 : 0] addra
    .dina                 (enqueue_head_infor_wr_data     ), // input [31 : 0] dina
    .douta                (enqueue_head_infor_rd_data     ), // output [31 : 0] douta
    .web                  (dequeue_head_infor_wr_en_b     ), // input [0 : 0] web
    .addrb                (dequeue_head_infor_wr_addr     ), // input [5 : 0] addrb
    .dinb                 (dequeue_head_infor_wr_data     ), // input [31 : 0] dinb
    .doutb                (dequeue_head_infor_rd_data     )
    // output [31 : 0] doutb
 );
//队尾信息RAM
queue_infor_ram_w16_d33_reg U_queue_tail_infor(
    .clk                  (clk                            ), // input clka
    .rst_n                (rst_n                          ), // input rst_n   
    .wea                  (enqueue_tail_infor_wr_en       ), // input [0 : 0] wea
    .addra                (enqueue_tail_infor_wr_addr     ), // input [5 : 0] addra
    .dina                 (enqueue_tail_infor_wr_data     ), // input [15 : 0] dina
    .douta                (enqueue_tail_infor_rd_data     ), // output [15 : 0] douta
    .web                  (dequeue_tail_wr_en_b           ), // input [0 : 0] web
    .addrb                (dequeue_tail_infor_wr_addr     ), // input [5 : 0] addrb
    .dinb                 (dequeue_tail_infor_wr_data     ), // input [15 : 0] dinb
    .doutb                (                               )
    // output [15 : 0] doutb
	);
//队长信息RAM
queue_infor_length_w16_d33_reg U_queue_length_infor(
    .clk                  (clk                            ), // input clka
    .rst_n                (rst_n                          ), 
    .wea                  (enqueue_length_infor_wr_en     ), // input [0 : 0] wea
    .addra                (enqueue_length_infor_wr_addr   ), // input [2 : 0] addra
    .dina                 (enqueue_length_infor_wr_data   ), // input [15 : 0] dina
    .douta                (enqueue_length_infor_rd_data   ), // output [15 : 0] douta
    .web                  (dequeue_length_infor_wr_en     ), // input [0 : 0] web
    .addrb                (dequeue_length_infor_wr_addr   ), // input [2 : 0] addrb
    .dinb                 (dequeue_length_infor_wr_data   ), // input [15 : 0] dinb
    .doutb                (dequeue_length_infor_rd_data   )
    // output [15 : 0] doutb
	);
//节点长度信息RAM
queue_infor_length_w16_d5_reg U_queue_node_length(
    .clk                  (clk                            ), // input clka
    .rst_n                (rst_n                          ),     
    .wea                  (enqueue_node_length_wr_en     ), // input [0 : 0] wea
    .addra                (enqueue_node_length_wr_addr   ), // input [2 : 0] addra
    .dina                 (enqueue_node_length_wr_data   ), // input [15 : 0] dina
    .douta                (enqueue_node_length_rd_data   ), // output [15 : 0] douta
    .web                  (dequeue_node_length_wr_en     ), // input [0 : 0] web
    .addrb                (dequeue_node_length_wr_addr   ), // input [2 : 0] addrb
    .dinb                 (dequeue_node_length_wr_data   ), // input [15 : 0] dinb
    .doutb                (dequeue_node_length_rd_data   )
    // output [15 : 0] doutb
	);
//物理队长RAM
// queue_infor_ram_w48_d5 U_queue_indicate_length(
//     .clka                 (clk                            ), // input clka
//     .wea                  (indicate_length_wren_a         ), // input [0 : 0] wea
//     .addra                (indicate_length_addr_a         ), // input [2 : 0] addra
//     .dina                 (indicate_length_din_a          ), // input [47 : 0] dina
//     .douta                (indicate_length_dout_a         ), // output [47 : 0] douta
//     .clkb                 (clk                            ), // input clkb
//     .web                  (indicate_length_wren_b         ), // input [0 : 0] web
//     .addrb                (indicate_length_addr_b         ), // input [2 : 0] addrb
//     .dinb                 (indicate_length_din_b          ), // input [47 : 0] dinb
//     .doutb                (indicate_length_dout_b         )
//     // output [47 : 0] doutb
//     );
//*********************
//MAIN CORE
//*********************
//队尾更新冲突避免
// always @(posedge clk or negedge rst_n) 
// begin
//     if (~rst_n)
//     begin
//         queue_tail_wren_a <= 1'b0;
//         queue_tail_din_a  <= 32'd0;
//         queue_tail_wren_b <= 1'b0;
//         queue_tail_din_b  <= 32'd0;    
//     end
//     else if (enqueue_tail_infor_wr_en == 1'b1 && dequeue_tail_infor_wr_en == 1'b1)      
//     begin
//         if(enqueue_tail_infor_wr_addr == dequeue_tail_infor_wr_addr)  // 同一队列同时更新队尾，队列里只有一帧，出队完成同时新帧入队完成，此时按照入队更新队尾
//         begin
//             queue_tail_wren_a <= 1'b1;
//             queue_tail_din_a  <= enqueue_tail_infor_wr_data;
//             queue_tail_wren_b <= 1'b0;
//             queue_tail_din_b  <= 32'd0;
//         end
//         else 
//         begin
//             queue_tail_wren_a <= enqueue_tail_infor_wr_en;
//             queue_tail_din_a  <= enqueue_tail_infor_wr_data;
//             queue_tail_wren_b <= dequeue_tail_infor_wr_en;
//             queue_tail_din_b  <= dequeue_tail_infor_wr_data;
//         end
//     end
//     else 
//     begin
//         queue_tail_wren_a <= enqueue_tail_infor_wr_en;
//         queue_tail_din_a  <= enqueue_tail_infor_wr_data;
//         queue_tail_wren_b <= dequeue_tail_infor_wr_en;
//         queue_tail_din_b  <= dequeue_tail_infor_wr_data;
//     end
// end

// //队长更新冲突避免
// assign queue_length_addr_a = enqueue_length_infor_wr_addr;
// assign queue_length_addr_b = dequeue_length_infor_wr_addr;

// always @(posedge clk or negedge rst_n) 
// begin
//     if (~rst_n)
//     begin
//         queue_length_wren_a <= 1'b0;
//         queue_length_din_a  <= 32'd0;
//         queue_length_wren_b <= 1'b0;
//         queue_length_din_b  <= 32'd0;    
//     end
//     else if(enqueue_length_infor_wr_addr == dequeue_length_infor_wr_addr)  //同一队列
//     begin
//         if(enqueue_length_infor_wr_en == 1'b1 && dequeue_length_infor_wr_en == 1'b1)             // 同时写
//         begin
//             queue_length_wren_a <= 1'b0;
//             queue_length_din_a  <= 32'd0;
//             queue_length_wren_b <= 1'b1;
//             queue_length_din_b  <= enqueue_length_infor_wr_data + dequeue_length_infor_wr_data - enqueue_length_infor_rd_data; 
//         end
//         else if(queue_length_wren_a == 1'b1 && dequeue_length_infor_wr_en == 1'b1)                                        //入队更新比出队更新队长操作早一个clk，
//         begin
//             queue_length_wren_a <= 1'b0;
//             queue_length_din_a  <= 32'd0;
//             queue_length_wren_b  <= 1'b1;
//             queue_length_din_b   <= queue_length_din_a + dequeue_length_infor_wr_data - dequeue_length_infor_rd_data; 
//         end
//         else if(queue_length_wren_b == 1'b1 && enqueue_length_infor_wr_en == 1'b1)                                    // 出队更新比入队更新早一个clk
//         begin
//             queue_length_wren_a  <= 1'b1;
//             queue_length_din_a   <= queue_length_din_b + enqueue_length_infor_wr_data - enqueue_length_infor_rd_data; 
//             queue_length_wren_b <= 1'b0;
//             queue_length_din_b  <= 32'd0;
//         end
//         else 
//         begin
//             queue_length_wren_a <= enqueue_length_infor_wr_en;
//             queue_length_din_a  <= enqueue_length_infor_wr_data;
//             queue_length_wren_b <= dequeue_length_infor_wr_en;
//             queue_length_din_b  <= dequeue_length_infor_wr_data; 
//         end
//     end
//     else 
//     begin
//         queue_length_wren_a <= enqueue_length_infor_wr_en;
//         queue_length_din_a  <= enqueue_length_infor_wr_data;
//         queue_length_wren_b <= dequeue_length_infor_wr_en;
//         queue_length_din_b  <= dequeue_length_infor_wr_data;   
//     end
// end

// always @(posedge clk or negedge rst_n) 
// begin
//     if (~rst_n) 
//     begin
//         queue_length_wren_a_r <= 1'b0;
//         queue_length_wren_b_r <= 1'b0;
//         queue_length_addr_a_r <= 6'd0;
//         queue_length_addr_b_r <= 6'd0;
//         queue_length_din_a_r <= 32'd0;
//         queue_length_din_b_r <= 32'd0;
//     end
//     else
//     begin
//         queue_length_wren_a_r <= queue_length_wren_a;
//         queue_length_wren_b_r <= queue_length_wren_b;    
//         queue_length_addr_a_r <= queue_length_addr_a;
//         queue_length_addr_b_r <= queue_length_addr_b;
//         queue_length_din_a_r <=  queue_length_din_a;
//         queue_length_din_b_r <=  queue_length_din_b;  
//     end
// end

// always @(*)
// begin
//     if(queue_length_addr_a_r == queue_length_addr_b_r)
//     begin
//         if(queue_length_wren_a_r == 1'b1 )
//         begin
//             enqueue_length_infor_rd_data = queue_length_din_a_r;
//             dequeue_length_infor_rd_data = queue_length_din_a_r;
//         end
//         else if(queue_length_wren_b_r == 1'b1)
//         begin
//             enqueue_length_infor_rd_data = queue_length_din_b_r;
//             dequeue_length_infor_rd_data = queue_length_din_b_r;
//         end
//         else 
//         begin
//             enqueue_length_infor_rd_data = queue_length_dout_a;
//             dequeue_length_infor_rd_data = queue_length_dout_b;
//         end
//     end
//     else 
//     begin
//         enqueue_length_infor_rd_data = queue_length_dout_a;
//         dequeue_length_infor_rd_data = queue_length_dout_b;
//     end
// end

// //节点长度更新冲突避免
// assign node_length_addr_a = enqueue_node_length_wr_addr;
// assign node_length_addr_b = dequeue_node_length_wr_addr;

// always @(posedge clk or negedge rst_n) 
// begin
//     if (~rst_n)
//     begin
//         node_length_wren_a <= 1'b0 ;
//         node_length_din_a  <= 16'd0;
//         node_length_wren_b <= 1'b0 ;
//         node_length_din_b  <= 16'd0;    
//     end
//     else if(enqueue_node_length_wr_addr == dequeue_node_length_wr_addr)   //同一队列
//     begin
//         if(enqueue_node_length_wr_en == 1'b1 && dequeue_node_length_wr_en == 1'b1)             // 同时更新 差额写入
//         begin
//             node_length_wren_a <= 1'b0;
//             node_length_din_a  <= 16'd0;
//             node_length_wren_b <= 1'b1;
//             node_length_din_b  <= enqueue_node_length_wr_data + dequeue_node_length_wr_data - enqueue_node_length_rd_data; 
//         end
//         else if(node_length_wren_a == 1'b1 && dequeue_node_length_wr_en == 1'b1)
//         begin
//             node_length_wren_a <= 1'b0;
//             node_length_din_a  <= 16'd0;
//             node_length_wren_b <= 1'b1;
//             node_length_din_b  <= node_length_din_a + dequeue_node_length_wr_data - dequeue_node_length_rd_data; 
//         end
//         else if(node_length_wren_b == 1'b1 && enqueue_node_length_wr_en == 1'b1)
//         begin
//             node_length_wren_a <= 1'b1;
//             node_length_din_a  <= node_length_din_b + enqueue_node_length_wr_data - enqueue_node_length_rd_data;
//             node_length_wren_b <= 1'b0 ;
//             node_length_din_b  <= 16'd0; 
//         end
//         else 
//         begin
//             node_length_wren_a <= enqueue_node_length_wr_en  ;
//             node_length_din_a  <= enqueue_node_length_wr_data;
//             node_length_wren_b <= dequeue_node_length_wr_en  ;
//             node_length_din_b  <= dequeue_node_length_wr_data; 
//         end
//     end
//     else 
//     begin
//         node_length_wren_a <= enqueue_node_length_wr_en  ;
//         node_length_din_a  <= enqueue_node_length_wr_data;
//         node_length_wren_b <= dequeue_node_length_wr_en  ;
//         node_length_din_b  <= dequeue_node_length_wr_data;  
//     end
// end

// always @(posedge clk or negedge rst_n) 
// begin
//     if (~rst_n) 
//     begin
//         node_length_wren_a_r <= 1'b0;
//         node_length_wren_b_r <= 1'b0;
//         node_length_addr_a_r <= 3'd0;
//         node_length_addr_b_r <= 3'd0;
//         node_length_din_a_r <= 16'd0;
//         node_length_din_b_r <= 16'd0;
//     end
//     else
//     begin
//         node_length_wren_a_r <= node_length_wren_a;
//         node_length_wren_b_r <= node_length_wren_b;  
//         node_length_addr_a_r <= node_length_addr_a;
//         node_length_addr_b_r <= node_length_addr_b;
//         node_length_din_a_r  <= node_length_din_a;
//         node_length_din_b_r  <= node_length_din_b;  
//     end
// end

// always @(*)
// begin
//     if(node_length_addr_a_r == node_length_addr_b_r)
//     begin
//         if(node_length_wren_a_r == 1'b1 )
//         begin
//             enqueue_node_length_rd_data = node_length_din_a_r;
//             dequeue_node_length_rd_data = node_length_din_a_r;
//         end
//         else if(node_length_wren_b_r == 1'b1)
//         begin
//             enqueue_node_length_rd_data = node_length_din_b_r;
//             dequeue_node_length_rd_data = node_length_din_b_r;
//         end
//         else 
//         begin
//             enqueue_node_length_rd_data = node_length_dout_a;
//             dequeue_node_length_rd_data = node_length_dout_b;
//         end
//     end
//     else 
//     begin
//         enqueue_node_length_rd_data = node_length_dout_a;
//         dequeue_node_length_rd_data = node_length_dout_b;
//     end
// end


//物理队长更新冲突避免
// assign indicate_length_addr_a = enqueue_indicate_length_wr_addr;
// assign indicate_length_addr_b = dequeue_indicate_length_wr_addr;

// always @(posedge clk or negedge rst_n) 
// begin
//     if (~rst_n)
//     begin
//         indicate_length_wren_a <= 1'b0 ;
//         indicate_length_din_a  <= 48'd0;
//         indicate_length_wren_b <= 1'b0 ;
//         indicate_length_din_b  <= 48'd0;    
//     end
//     else if(enqueue_indicate_length_wr_addr == dequeue_indicate_length_wr_addr)   //同一队列
//     begin
//         if(enqueue_indicate_length_wr_en == 1'b1 && dequeue_indicate_length_wr_en == 1'b1)             // 同时更新 差额写入
//         begin
//             indicate_length_wren_a <= 1'b0;
//             indicate_length_din_a  <= 48'd0;
//             indicate_length_wren_b <= 1'b1;
//             indicate_length_din_b  <= enqueue_indicate_length_wr_data + dequeue_indicate_length_wr_data - enqueue_indicate_length_rd_data; 
//         end
//         else if(indicate_length_wren_a == 1'b1 && dequeue_indicate_length_wr_en == 1'b1)
//         begin
//             indicate_length_wren_a <= 1'b0;
//             indicate_length_din_a  <= 48'd0;
//             indicate_length_wren_b <= 1'b1;
//             indicate_length_din_b  <= indicate_length_din_a + dequeue_indicate_length_wr_data - dequeue_indicate_length_rd_data; 
//         end
//         else if(indicate_length_wren_b == 1'b1 && enqueue_indicate_length_wr_en == 1'b1)
//         begin
//             indicate_length_wren_a <= 1'b1;
//             indicate_length_din_a  <= indicate_length_din_b + enqueue_indicate_length_wr_data - enqueue_indicate_length_rd_data;
//             indicate_length_wren_b <= 1'b0 ;
//             indicate_length_din_b  <= 48'd0; 
//         end
//         else 
//         begin
//             indicate_length_wren_a <= enqueue_indicate_length_wr_en  ;
//             indicate_length_din_a  <= enqueue_indicate_length_wr_data;
//             indicate_length_wren_b <= dequeue_indicate_length_wr_en  ;
//             indicate_length_din_b  <= dequeue_indicate_length_wr_data; 
//         end
//     end
//     else 
//     begin
//         indicate_length_wren_a <= enqueue_indicate_length_wr_en  ;
//         indicate_length_din_a  <= enqueue_indicate_length_wr_data;
//         indicate_length_wren_b <= dequeue_indicate_length_wr_en  ;
//         indicate_length_din_b  <= dequeue_indicate_length_wr_data;  
//     end
// end

// always @(posedge clk or negedge rst_n) 
// begin
//     if (~rst_n) 
//     begin
//         indicate_length_wren_a_r <= 1'b0;
//         indicate_length_wren_b_r <= 1'b0;
//         indicate_length_addr_a_r <= 3'd0;
//         indicate_length_addr_b_r <= 3'd0;
//         indicate_length_din_a_r <= 48'd0;
//         indicate_length_din_b_r <= 48'd0;
//     end
//     else
//     begin
//         indicate_length_wren_a_r <= indicate_length_wren_a;
//         indicate_length_wren_b_r <= indicate_length_wren_b;  
//         indicate_length_addr_a_r <= indicate_length_addr_a;
//         indicate_length_addr_b_r <= indicate_length_addr_b;
//         indicate_length_din_a_r  <= indicate_length_din_a;
//         indicate_length_din_b_r  <= indicate_length_din_b;  
//     end
// end

// always @(*)
// begin
//     if(indicate_length_addr_a_r == indicate_length_addr_b_r)
//     begin
//         if(indicate_length_wren_a_r == 1'b1 )
//         begin
//             enqueue_indicate_length_rd_data = indicate_length_din_a_r;
//             dequeue_indicate_length_rd_data = indicate_length_din_a_r;
//         end
//         else if(indicate_length_wren_b_r == 1'b1)
//         begin
//             enqueue_indicate_length_rd_data = indicate_length_din_b_r;
//             dequeue_indicate_length_rd_data = indicate_length_din_b_r;
//         end
//         else 
//         begin
//             enqueue_indicate_length_rd_data = indicate_length_dout_a;
//             dequeue_indicate_length_rd_data = indicate_length_dout_b;
//         end
//     end
//     else 
//     begin
//         enqueue_indicate_length_rd_data = indicate_length_dout_a;
//         dequeue_indicate_length_rd_data = indicate_length_dout_b;
//     end
// end

(*mark_debug = "true"*) reg [31:0] enqueue_length_infor_cnt;
always @(posedge clk or negedge rst_n) begin
	if (~rst_n) begin
		enqueue_length_infor_cnt <= 32'd0;
	end
	else if (enqueue_length_infor_wr_en) begin
		enqueue_length_infor_cnt <= enqueue_length_infor_cnt + 1'b1;
	end
	else begin
		enqueue_length_infor_cnt <= enqueue_length_infor_cnt;
	end
end
(*mark_debug = "true"*) reg [31:0] dequeue_length_infor_cnt;
always @(posedge clk or negedge rst_n) begin
	if (~rst_n) begin
		dequeue_length_infor_cnt <= 32'd0;
	end
	else if (dequeue_length_infor_wr_en) begin
		dequeue_length_infor_cnt <= dequeue_length_infor_cnt + 1'b1;
	end
	else begin
		dequeue_length_infor_cnt <= dequeue_length_infor_cnt;
	end
end
(*mark_debug = "true"*) reg [31:0] enqueue_node_length_cnt;
always @(posedge clk or negedge rst_n) begin
	if (~rst_n) begin
		enqueue_node_length_cnt <= 32'd0;
	end
	else if (enqueue_node_length_wr_en) begin
		enqueue_node_length_cnt <= enqueue_node_length_cnt + 1'b1;
	end
	else begin
		enqueue_node_length_cnt <= enqueue_node_length_cnt;
	end
end
(*mark_debug = "true"*) reg [31:0] dequeue_node_length_cnt;
always @(posedge clk or negedge rst_n) begin
	if (~rst_n) begin
		dequeue_node_length_cnt <= 32'd0;
	end
	else if (dequeue_node_length_wr_en) begin
		dequeue_node_length_cnt <= dequeue_node_length_cnt + 1'b1;
	end
	else begin
		dequeue_node_length_cnt <= dequeue_node_length_cnt;
	end
end
endmodule